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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">GICD_SGIR, Software Generated Interrupt Register</h1><p>The GICD_SGIR characteristics are:</p><h2>Purpose</h2>
        <p>Controls the generation of SGIs.</p>
      <h2>Configuration</h2>
        <p>This register is available in all configurations of the GIC. If the GIC supports two Security states this register is Common.</p>
      <h2>Attributes</h2>
        <p>GICD_SGIR is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="6"><a href="#fieldset_0-31_26">RES0</a></td><td class="lr" colspan="2"><a href="#fieldset_0-25_24">TargetListFilter</a></td><td class="lr" colspan="8"><a href="#fieldset_0-23_16">CPUTargetList</a></td><td class="lr" colspan="1"><a href="#fieldset_0-15_15">NSATT</a></td><td class="lr" colspan="11"><a href="#fieldset_0-14_4">RES0</a></td><td class="lr" colspan="4"><a href="#fieldset_0-3_0">INTID</a></td></tr></tbody></table><h4 id="fieldset_0-31_26">Bits [31:26]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-25_24">TargetListFilter, bits [25:24]</h4><div class="field">
      <p>Determines how the Distributor processes the requested SGI.</p>
    <table class="valuetable"><tr><th>TargetListFilter</th><th>Meaning</th></tr><tr><td class="bitfield">0b00</td><td>
          <p>Forward the interrupt to the CPU interfaces specified by GICD_SGIR.CPUTargetList.</p>
        </td></tr><tr><td class="bitfield">0b01</td><td>
          <p>Forward the interrupt to all CPU interfaces except that of the PE that requested the interrupt.</p>
        </td></tr><tr><td class="bitfield">0b10</td><td>
          <p>Forward the interrupt only to the CPU interface of the PE that requested the interrupt.</p>
        </td></tr><tr><td class="bitfield">0b11</td><td>
          <p>Reserved.</p>
        </td></tr></table></div><h4 id="fieldset_0-23_16">CPUTargetList, bits [23:16]</h4><div class="field"><p>When GICD_SGIR.TargetListFilter is <span class="binarynumber">0b00</span>, this field defines the CPU interfaces to which the Distributor must forward the interrupt.</p>
<p>Each bit of the field refers to the corresponding CPU interface. For example, CPUTargetList[0] corresponds to interface 0. Setting a bit to 1 indicates that the interrupt must be forwarded to the corresponding interface.</p>
<p>If this field is <span class="binarynumber">0b00000000</span> when GICD_SGIR.TargetListFilter is <span class="binarynumber">0b00</span>, the Distributor does not forward the interrupt to any CPU interface.</p></div><h4 id="fieldset_0-15_15">NSATT, bit [15]</h4><div class="field">
      <p>Specifies the required group of the SGI.</p>
    <table class="valuetable"><tr><th>NSATT</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 0 on that interface.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Forward the SGI specified in the INTID field to a specified CPU interface only if the SGI is configured as Group 1 on that interface.</p>
        </td></tr></table>
      <p>This field is writable only by a Secure access. Non-secure accesses can also generate Group 0 interrupts, if allowed to do so by GICD_NSACR0. Otherwise, Non-secure writes to GICD_SGIR generate an SGI only if the specified SGI is programmed as Group 1, regardless of the value of bit [15] of the write.</p>
    </div><h4 id="fieldset_0-14_4">Bits [14:4]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-3_0">INTID, bits [3:0]</h4><div class="field">
      <p>The INTID of the SGI to forward to the specified CPU interfaces.</p>
    </div><h2>Accessing GICD_SGIR</h2>
        <p>This register is used only when affinity routing is not enabled. When affinity routing is enabled, this register is <span class="arm-defined-word">RES0</span>.</p>

      
        <p>It is <span class="arm-defined-word">IMPLEMENTATION DEFINED</span> whether this register has any effect when the forwarding of interrupts by the Distributor is disabled by <a href="ext-gicd_ctlr.html">GICD_CTLR</a>.</p>
      <h4>GICD_SGIR can be accessed through the memory-mapped interfaces:</h4><table class="info"><tr><th>Component</th><th>Frame</th><th>Offset</th><th>Instance</th></tr><tr><td>GIC Distributor</td><td>Dist_base</td><td><span class="hexnumber">0x0F00</span></td><td>GICD_SGIR</td></tr></table><p>Accesses on this interface are <span class="access_level">WO</span>.</p><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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